In recent years, with the advances made in the miniaturization of electronic devices, integration densities of IC (SSI, MSI, LSI AND VLSI) chips have been greatly increased. In mounting of semiconductor devices, such as ICs, onto a substrate, the distance (pitch) between electrode bumps (bumps) has been reduced while the number of input/output(I/O) terminals has been increased. In card type calculators and IC cards, a demand has arisen for developing low-profile products which require short pitches.
Wireless bonding, such as tape automated bonding (TAB) and flip chip, can advantageously realize collective bonding of bumps with high-precision alignment between the bumps, low-profile automatic mounting of semiconductor elements, and high reliability. Therefore, wireless bonding has become a mainstream mounting technique for LSI chips.
In performing wireless bonding, metal projections known as electrode bumps are generally formed on a substrate or on input/output pads of IC chips. The present methods for creating these bumps suffer from several drawbacks. Obtaining a bump aspect (height/width) ratio of greater than 1.5/1 is difficult to achieve. Relative bump positional tolerances are not satisfactory. Flip chip bond verification cannot be easily accomplished and the bump contact resistance is high. A further problem is Temperature Coefficient of Expansion (TCE) mismatch between the substrate and the semiconductor die mounted to the substrate. For example, for many applications the IBM C4 process is nonacceptable for Die greater than approximately 600 mils due to TCE mismatch. This problem is exacerbated in I/O pads located in corners of the substrate because shear forces due to TCE mismatch are in multiple directions.